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Previous: Basic Bandgap Voltage Reference Structure

Error Sources

To achieve good accuracy of any bandgap voltage reference it is necessary to define the main contributors into the total accuracy error [4]. Following are the largest contributors of the proposed architecture:

  • amplifier offset voltage
  • mismatch between resistors R1 and R2
  • saturation current mismatch of bipolar transistor
  • variation of the resistors R1, R2 and R3

Amplifier Offset Voltage

The amplifier offset voltage is critical for reference voltage accuracy because it is amplified by the same method as the emitter base voltage difference. While we can reduce the influence of amplifier offset voltage increase of the area ratio between bipolar transistors, we are limited by reasonable value of this ratio because the voltage difference has logarithmic scale. For our case we selected the ratio 24.

The most influence on the amplifier offset voltage is the input stage transistors threshold voltage variation. It can be improved by increasing the size of an amplifier input pair (Equation 6).

Mismatch Between Resistors R1 & R2

The ratio between resistors R1 and R2 defines the gain of the positive temperature coefficient term in Equation 5. In order for this gain coefficient to be accurate, we use relatively large area unit resistors. Using a special layout for the resistors, the ratio accuracy of 0.1% can be achieved.

Resistors & Saturation Current of Bipolar Transistor Variation

Both variations lead to a shift of the base emitter voltage of bipolar transistor, Veb. The base emitter voltage can be determined as Equation 7:

where I is the emitter current and IS is the saturation current of a bipolar transistor. IS variation is mostly caused by the mismatching of Q1 and Q2 transistor areas and impurity concentration variation.

Variation of resistor R1 affects the absolute value of the current I though transistor Q2, which is the part of the negative temperature coefficient term, VEB.

Resistors R2 and R3 determine the current through Q1 and Q2, respectively. Variation of R2 and R3 causes inaccuracy of the positive temperature coefficient term of the reference voltage (Equation 5). However, an error caused by this variation can be reduced by good matching of resistors R2 and R3.

High PSRR Bandgap Voltage Reference Circuit

Taking into account all drawbacks of the conventional voltage reference architecture discussed above we are proposing an improved voltage reference, which is a combination of bandgap voltage reference with a low dropout regulator (Figure 6).

 Figure 6. Block diagram of a bandgap voltage reference combined with a low dropout regulator.

The output voltage in this case can be determined by Equaiton 8:

VREF node is the output node of the bandgap reference and supply line of the bandgap core simultaneously. This allows us to protect the bandgap core from the supply voltage ripple with an LDO.

To achieve small quiescent current the values of resistors R1, R2, R3 and R4 are relatively large – 8 MOhms for the proposed circuit. This allows the current through Q1 and Q2 to be reduced down to 40 nA. The overall quiescent current of the proposed architecture is 250 nA. In addition to this we use a bias current source with quiescent current of 100 nA.

Bias Current Circuit

The proposed bias current circuitry is based on a well-known structure shown in Figure 7, and described in detail in Reference 5.[5]

In this circuit two n-type transistors, M5 and M7, form the first current mirror with the gain S7/S5. Two p-type transistors, M4 and M6, form the first current mirror with the gain S4/S6, where the S4, S5, S6 and S7 are the area of corresponding transistors.

Typically a bias generator does not require special startup circuitry, which could reduce quiescent current and occupied area. If the current is small enough, the resistance R can be neglected. Two current mirrors formed by M5/M7 and M4/M6 are interconnected into a closed loop.

The gain of this loop is larger than unity, so currents in both branches increase until equilibrium is reached. This is defined by the voltage drop across resistor R and can be presented as Equation 9:

Figure 7. Bias generator with dynamic startup current

To accelerate startup time and avoid the possible leakage influence, an additional startup circuit is used. The transistor M0 is used as a lateral bipolar NPN transistor with very large resistance, which minimizes the startup current. Capacitor C provides fast transient startup when a circuit is powered on and prevents oscillation of the startup circuitry. After startup the circuitry is blocked by the transistor M2. The bias current of bias block is 40 nA. The total current consumption is 80 nA.

Verification Results

The proposed bandgap reference is used in the ultralow noise, high PSRR low dropout regulator and implemented in CMOS 9T5V technology. The PSRR value is presented in Figure 8. Monte Carlo and temperature variation simulation results for output voltage accuracy are presented in Figure 9. The measurement results can be found in Table 1.

Figure 8.  PSRR of voltage reference source

Figure 9. Output voltage accuracy

Table 1. Measurement data

 

Parameter

Typical

Unit

Temperature range

–40°C to 125°C

°C

Quiescent current

250

nA

Output voltage

1.206

V

Output voltage accuracy (1σ)

0.5

%

Output voltage temperature coefficient

15

ppm/°C

PSRR @100Hz

93

dB

Startup time

90

us

 

Summary

A high-PSRR, extremely low-power bandgap voltage reference implemented in CMOS9T5V 0.18-µm process has been presented. The design conditions to minimize the power consumption and maximize PSRR have been described in detail. Combining a bandgap voltage reference with a low dropout regulator allows us to obtain high PSRR of 93 dB at 100 Hz. The maximum quiescent current of only 250 nA makes the circuit very attractive for ultra-low-power applications.

References

  1. J. Guo and K. N. Leung, “A 6-uW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,” IEEE Journal of Solid State Circuits, vol.48, No.9, Sep. 2010
  2. Blakiewicz, G., "CMOS low-dropout regulator with improved time response," Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference , vol., no., pp.279,282, 16-18 June 2011
  3. P. Hazucha, T. Karnik, B. A. Bloecher, C. Parsons, D. Finan and S. Borkar, “Area-Efficient Linear Regulator With Ultra-Fast load regulation,” IEEE Journal of Solid State Circuits, vol. 45, No.4, Apr. 2005
  4. S. Strik, “Bandgap voltage reference: errors and techniques for their minimization,” Proceedings of BEC 2006, pp. 123-126, Oct. 2, 2006
  5. E. Vittoz, J. Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation,” IEEE Journal of Solid State Circuits, vol. SC-12, No.3, Jun. 1977
  6. For more information about LDOs, visit: www.ti.com/ldo-ca.
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