The SPEAr1300 features 64-bit AXI (AMBA3) bus Network-on-Chip technology.
STMicroelectronics (Carrollton, TX) (NYSE: STM) has revealed the new architecture that will be the backbone for the new members of its popular SPEAr (Structured Processor Enhanced Architecture) family of embedded microprocessors, targeting high-performance connectivity and embedded applications. The SPEAr1300 features:
- Dual ARM Cortex-A9 cores, running at 600MHz for 3000 DMIPS equivalent.
- 64-bit AXI (AMBA3) bus Network-on-Chip technology.
- DRAM and L2 cache with Error Correction Code (ECC).
- 533MHz 32-bit DDR3 memory controllers with ECC; 16-bit DDR2 also supported.
- Accelerator coherence port.
- Gigabit Ethernet.
- PCIe 2.0 supporting 5 GT/s (Gigatransfers/second).
- SATA II 3 Gbit/s.
- USB 2.0.
- 256-bit key hardware encryption/decryption.
- 1.3 million gates of configurable logic.
For more information visit www.st.com
ADVERTISEMENT